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SC1405D
POWER MANAGEMENT
Applications Information (Cont.)
could exceed device’s absolute maximum rating of 8V.
To eliminate the effect of the ringing on the boost
capacitor voltage, place a 4.7 - 10 Ohm resistor between
boost Schottky diode and Vcc to filter the negative spikes
on DRN Pin. Alternately, a Silicon diode, such as the
commonly available 1N4148 can substitute for the
Schottky diode and eliminate the need for the series re-
sistor.
Proper layout will guarantee minimum ringing and elimi-
nate the need for external components. Use of SO-8 or
other surface mount FETs will reduce lead inductance
and their parasitic effects.
ASYNCHRONOUS OPERATION
The SC1405D can be configured to operate in Asynchro-
nous mode by pulling S-MOD to logic LOW, thus disabling
the bottom FET drive. This has the effect of saving power
at light loads since the bottom FET’s gate capacitance
does not have to charged at the switching frequency.
There can be a significant savings since the bottom driver
can supply up to 2A pulses to the FET at the switching
frequency. There is an additional efficiency benefit to
operating in asynchronous mode. When operating in syn-
chronous mode, the inductor current can go negative
and flow in reverse direction when the bottom FET is on
and the DC load is less than 1/2 inductor ripple current.
At that point, the inductor core and wire losses, depend-
ing on the magnitude of the ripple current, can be quite
significant. Operating in asynchronous mode at light loads
effectively only charges the inductor by as much as
needed to supply the load current, since the inductor
never completely discharges at light loads. DC regula-
tion can be an issue when operating in asynchronous
mode, depending on the type of controller used and mini-
mum load required to maintain regulation. If there are
no Shottkey diodes used in parallel with bottom FET, the
FET’s body diode will need to conduct in asynchronous
mode. The high voltage drop of this diode must be con-
sidered when determining the criteria for this mode of
operation.
DSPS DR
This pin produces an output which is a logical duplicate
of the bottom FET’s gate drive, if S-MOD is held High.
OVP_S/OVER TEMP SHUTDOWN
Output over-voltage protection (OVP) may be implemented
on the SC1405D independent of the PWM controller . A
voltage divider from the output is compared with the in-
ternal bandgap voltage of 1.2V (typical). Upon exceeding
this voltage, the overvoltage comparator disables the top
FET, while turning on the bottom FET to allow discharge
of the output capacitors excessive voltage through the
output inductor.
The SC1405D has a unique adaptive OVP circuit. Short
noise pulses, less than ~100ns are rejected completely;
longer pulses will trigger OVP if only of sufficient magni-
tude. A long term transient will trigger OVP with a smaller
magnitude. To assure proper tripping, bypass the resis-
tor from OVP_S pin to GND with a capacitor. The value of
this capacitor must be selected to achieve a time con-
stant equal to one switching period. Leave at least 250mV
headroom on the OVP pin to prevent false OVP events.
The SC1405D will shutdown if its T J exceeds 165°C.
? 2005 Semtech Corp.
9
www.semtech.com
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